PCBdesignforreduceEMI(pdf 23)

Contents
Title Page
ABSTRACT . . . . .  . 1
1 Background. . . .. . . . . 1
1.1 RF Sources. . . .. .. . 1
1.2 Surface-Mount Devices vs Through-Hole Components. .. . . 1
1.3 Static Pins vs Active Pins vs Inputs. .. 1
1.4 Basic Loops. . . .. .. . 2
1.4.1 Proportionality of Loops and Dipoles . .. . . . 3
1.5 Differential vs Common Mode. . . .. . 3
2 Board Layout. . . .. . . . 4
2.1 Grounds and Power. . . ... .. 4
2.1.1 Inductance. . . ... .. . 4
2.1.2 Two-Layer vs Four-Layer Boards . . . . . . 4
2.1.3 Microcomputer Grounds in One- and Two-Layer Designs . .. . . . . 5
2.1.4 Signal Return Grounds. . . .. . 5
2.1.5 Analog vs Digital vs High Power . . . . . . 5
2.1.6 Analog Power-Supply Pins and Analog Reference Voltages . .. . . . 6
2.1.7 Power Plane Do’s and Dont’s for Four-Layer Boards . . . . . . . 6
2.2 Power Distribution for Two-Layer Boards . .. . 7
2.2.1 Single-Point vs Multipoint Distribution . .. . . 7
2.2.2 Star Distribution. . . .. . . . . . . 7
2.2.3 Gridding to Create Planes. . . .7
2.2.4 Bypassing and Ferrite Beads. .9
2.2.5 Keeping Noise Close to the Chip . .. . . . . . . 11
2.3 Board Zoning. . . ... .12
2.4 Signal Traces. . . .. .13
2.4.1 Capacitive and Inductive Crosstalk . .. . . . . 13
2.4.2 Antenna Factor Length Rules . . . . . . . . 13
2.4.3 Series Termination, Transmission Lines . .. . 13
2.4.4 Impedance Matching at Inputs . . . . . . . 14
2.5 Cables and Connectors. . . .. . . . . . . 14
2.5.1 Differential-Mode and Common-Mode Noise. .. . . 14
2.5.2 Crosstalk Model. . . .. . . . . . 14
2.5.3 Number of Returns. . . .. . . . 15
2.5.4 I/O Recommendations for Off-PCB Signals. .. . . . 15
2.5.5 Keeping Noise and Electrostatic Discharge (ESD) Out . . . . . 15
2.6 Other Layout Issues. . . ... .15
2.6.1 Front-Panel PCB with Keypad and 某公司 in Automotive and Consumer Applications. .. . . . 15
2.6.2 Layout for Susceptibility. .. . 16
2.6.3 Autorouters. . . ... .16
3 Shielding. . . .. . . . . . . 17
3.1 How It Works. . . ... . . 17
3.2 Grounding the Shield. . . .. . . . . . . . 17
3.3 Cables and Bypassing to the Shield. .17
3.4 Slot Antennas: Cooling Slots and Seams . .. . . . . . . 18
4 Summary. . . .. . . . . . . 18
5 Literature. . . .. . . . . . 19
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List of Illustrations
Figure Title Page
1 Signals Below 50 kHz Are Not EMI Concerns . .. . . . . 2
2 Examples of Loops. . . ... .. . 3
3 Differential vs Common-Mode Noise. .. 4
4 Microcomputer Ground. . . .. . . . . . . . . 5
5 Layout Considerations. . . ... .6
6 Power Distribution. . . ... . 7
7 Gridding Power Traces on Two-Layer Boards . .. . . . . 8
8 Gridding of Ground Fills and Traces to Form a Ground Plane . . . . . . . . 9
9 Ferrite-Bead Placement Closest to the Noise Source. .. . . . . 10
10 Board Zoning. . . .. .. 12
11 MOS Buffer Simplified Schematic. .. . 14
12 Front-Panel Gridding to Form Two Ground Planes . .16
13 Mounting Filter Capacitors for External I/Os . .. . . . . 18
List of Tables
Table Title Page
1 Termination Characteristics. . . .. . . . . 13
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