MC68HC58数据链路控制器(pdf 102页)(英文)

2.1 MC68HC58 DLC Parallel Mode ................................................................2-1
2.1.1 DLC Parallel Mode Pin Function .......................................................2-2
2.1.1.1 ADDR0 — Address bit ..............................................................2-2
2.1.1.2 BUS — SAE J1850 Multiplex Bus .............................................2-2
2.1.1.3 CS — DLC Chip-Select .............................................................2-2
2.1.1.4 DATA[7:0] — DLC Data Bus .....................................................2-3
2.1.1.5 ECLK — 6800 Bus Clock ..........................................................2-3
2.1.1.6 INT — DLC Interrupt REQuest ...................................................2-3
2.1.1.7 LITO — Logic In Transceiver Out .............................................2-3
2.1.1.8 LOAD — External Bus LOAd .....................................................2-3
2.1.1.9 LOTI — Logic Out Transceiver In .............................................2-3
2.1.1.10 OSC1, OSC2 — External Oscillator ..........................................2-3
2.1.1.11 PRLMD — Parallel Mode ..........................................................2-3
2.1.1.12 PSEN — Power Supply Enable ................................................2-3
2.1.1.13 RST — DLC Reset ....................................................................2-4
2.1.1.14 REXT — External bias Resistor ................................................2-4
2.1.1.15 R/W — Read/WrITe Strobe ........................................................2-4
2.1.1.16 V
BATT
— Battery Voltage ..........................................................2-4
2.1.1.17 V
CC
— Analog Power Supply Voltage ......................................2-4
2.1.1.18 VDD — DigITal Power Supply Voltage .......................................2-4
2.1.1.19 VSSA — Analog Power Ground ................................................2-4
2.1.1.20 VSSD — DigITal Power Ground .................................................2-4
2.1.2 Example DLC Parallel Mode System ................................................2-5
2.2 MC68HC58 DLC Serial Mode ...................................................................2-7
2.2.1 DLC Serial Mode Pin Function ..........................................................2-7
2.2.1.1 BUS — SAE J1850 Multiplex Bus .............................................2-7
2.2.1.2 CS — DLC Chip-Select .............................................................2-7
2.2.1.3 INT — DLC Interrupt REQuest ...................................................2-8
2.2.1.4 LITO — Logic In Transceiver Out .............................................2-8
2.2.1.5 LOAD — External Bus LOAd .....................................................2-8
2.2.1.6 LOTI — Logic Out Transceiver In .............................................2-8
2.2.1.7 OSC1, OSC2 — External Oscillator ..........................................2-8
2.2.1.8 PRLMD —Parallel Mode ...........................................................2-8
2.2.1.9 PSEN — Power Supply Enable ................................................2-8
2.2.1.10 RST — DLC Reset ....................................................................2-8
2.2.1.11 REXT — External bias Resistor ................................................2-8
2.2.1.12 SCLK — Serial Clock ................................................................2-9
2.2.1.13 SIMO — Slave In Master Out ....................................................2-9
2.2.1.14 SOMI — Slave Out Master In ....................................................2-9
2.2.1.15 VBATT — Battery Voltage ........................................................2-9
2.2.1.16 VCC — Analog Power Supply Voltage .....................................2-9
2.2.1.17 VDD — DigITal Power Supply Voltage .......................................2-9
2.2.1.18 VSSA — Analog Power Ground ................................................2-9
2.2.1.19 VSSD — DigITal Power Ground .................................................2-9
2.2.2 Example DLC Serial Mode System .................................................2-10
2.3 Bus LOAding ............................................................................................2-12
2.4 DLC Clock Sources .................................................................................2-12
2.4.1 Logic Clock ......................................................................................2-12
2.4.2 Host Interface Clock ........................................................................2-12
2.5 Power Supply Connections .....................................................................2-13
2.5.1 Method 1 — All Supplies ApplIEd ....................................................2-14
2.5.2 Method 2 — Switching VDD WITh PSEN .........................................2-15
2.5.3 Method 3 — SwITching VDD and VCC Simultaneously ...................2-16
2.6 Reset .......................................................................................................2-17
SECTION 3 J1850 FRAME FORMAT
3.1 J1850 Frame Format .................................................................................3-1
3.1.1 SOF — Start of Frame Symbol .........................................................3-2
3.1.2 Data — In Frame Data Bytes ............................................................3-2
3.1.2.1 Logic Zero .................................................................................3-3
3.1.2.2 Logic One ..................................................................................3-3
3.1.3 CRC — Cyclical Redundancy Check Byte ........................................3-3
3.1.4 EOD — End of Data Symbol .............................................................3-3
3.1.5 NB — Normalization bit .....................................................................3-3
3.1.6 IFR — In-Frame Response Bytes .....................................................3-4
3.1.7 EOF — End of Frame Symbol ...........................................................3-4
3.1.8 IFS — Inter-Frame Separation Symbol .............................................3-4
3.1.9 BREAK — Break ...............................................................................3-4
3.1.10 Idle Bus .............................................................................................3-5
3.2 J1850 VPW Valid/Invalid bits and Symbols ..............................................3-5
3.2.1 Invalid Passive bit .............................................................................3-7
3.2.2 Valid Passive Logic Zero ...................................................................3-7
3.2.3 Valid Passive Logic One ...................................................................3-7
3.2.4 Valid EOD Symbol .............................................................................3-7
3.2.5 Valid EOF and IFS Symbol ...............................................................3-7
3.2.6 Idle Bus .............................................................................................3-7
3.2.7 Invalid Active bit ................................................................................3-7
3.2.8 Valid Active Logic One ......................................................................3-8
3.2.9 Valid Active Logic Zero ......................................................................3-8
3.2.10 Valid SOF Symbol .............................................................................3-9
3.2.11 Valid BREAK Symbol ........................................................................3-9
3.3 Frame Arbitration .......................................................................................3-9
SECTION 4 DATA LINK CONTROLLER OPERATION
4.1 Operating Modes .......................................................................................4-1
4.1.1 Power-Off Mode ................................................................................4-2
4.1.2 Reset Mode .......................................................................................4-2
4.1.3 Normal Mode .....................................................................................4-2
4.1.4 Standby Mode ...................................................................................4-2
4.1.5 4X Mode ............................................................................................4-2
4.1.6 Block Mode ........................................................................................4-3
4.2 Host Interface ............................................................................................4-3
4.2.1 MC68HC58 DLC Parallel Mode Host MCU Interface ........................4-5
4.2.1.1 Parallel Mode Data Transfer .....................................................4-5
4.2.1.2 Servicing SEQuence ..................................................................4-6
4.2.1.3 Minimum Time REQuirements ...................................................4-7
4.2.1.4 Motorola Microcontroller Data Transfers ...................................4-7
4.2.2 MC68HC58 DLC Serial Mode Host MCU Interface ...........................4-8
4.2.2.1 Serial Mode Data Transfer ........................................................4-8
4.2.2.2 Servicing SEQuence ..................................................................4-9
4.2.2.3 SPI Exchange ...........................................................................4-9
4.2.2.4 InITialization .............................................................................4-10
4.2.3 Interrupt REQuests ...........................................................................4-11
4.3 TransmITter Operation .............................................................................4-12
4.4 Receiver Operation .................................................................................4-16
4.5 Block Mode Operation .............................................................................4-20
4.6 BREAK Operation ...................................................................................4-21
4.7 In-Frame Response (IFR) .......................................................................4-21
SECTION 5 CONTROL AND STATUS CODES
5.1 Command Byte ..........................................................................................5-1
5.1.1 GCOM[7:5] — General Command FIEld ...........................................5-1
5.1.1.1 Do Nothing ................................................................................5-2
5.1.1.2 Enter Standby Mode .................................................................5-2
5.1.1.3 Send BREAK Symbol ................................................................5-2
5.1.1.4 Send IFR on EOD wITh CRC .....................................................5-2
5.1.1.5 Terminate Auto Retry ................................................................5-3
5.1.1.6 Send IFR on EOD wIThout CRC ................................................5-3
5.1.1.7 Abort Transmission ...................................................................5-4
5.1.2 BTAD[4:2] — Byte Type and Destination FIEld .................................5-4
5.1.2.1 Do Not LOAd ..............................................................................5-4
5.1.2.2 LOAd as TransmIT Data ..............................................................5-4
5.1.2.3 LOAd as Last Byte of TransmIT Data ..........................................5-5
5.1.2.4 LOAd as Configuration Byte .......................................................5-5
5.1.2.5 LOAd as First Byte of TransmIT Data ..........................................5-5
5.1.2.6 LOAd as Configuration Byte – Immediate ..................................5-5
5.1.2.7 LOAd as First and Last Byte of Frame .......................................5-6
5.1.3 RFC[1:0] — Receive FIFO Command FIEld ......................................5-6
5.1.3.1 Do Nothing ................................................................................5-6
5.1.3.2 Flush Byte .................................................................................5-6
5.1.3.3 Flush Frame ..............................................................................5-6
5.2 Configuration Byte .....................................................................................5-7
5.2.1 TM — Test Mode Control bit .............................................................5-7
5.2.2 TC[6:5] — Test Configuration FIEld ...................................................5-7
5.2.3 IMSK — Interrupt Mask bit ................................................................5-7
5.2.4 IMOD — Interrupt Mode bit ...............................................................5-8
5.2.5 OSCD[2:1] — Oscillator Divisor FIEld ................................................5-8
5.2.6 4X — High-Speed Control bit ............................................................5-8
5.3 Status Byte ................................................................................................5-8
5.3.1 RFS[7:5] — Receive FIFO Status FIEld ............................................5-9
5.3.1.1 Buffer Invalid or Empty ..............................................................5-9
5.3.1.2 Buffer Contains More Than One Byte .......................................5-9
5.3.1.3 Buffer Contains a Completion Code ..........................................5-9
5.3.1.4 Thirteenth Byte Received ..........................................................5-9
5.3.1.5 One Byte in Buffer ...................................................................5-10
5.3.1.6 Completion Code at Head of Buffer, More Bytes Available ....5-10
5.3.1.7 Completion Code at Head of Buffer, Frame Available ............5-10
5.3.1.8 Completion Code Only at Head of Buffer ................................5-10
5.3.2 DLI — Data Link Idle bit ..................................................................5-10
5.3.3 NETF — Network Fault bit ..............................................................5-10
5.3.4 4XMD — 4X Mode bit .....................................................................5-11
5.3.5 TMFS[1:0] — TxFIFO Status FIEld ..................................................5-11
5.3.5.1 Buffer Empty ...........................................................................5-11
5.3.5.2 Buffer Contains Data ...............................................................5-11
5.3.5.3 Buffer Almost Full ....................................................................5-11
5.3.5.4 Buffer Full ................................................................................5-11
5.4 Completion Code Byte ............................................................................5-11
5.4.1 ERRF — Error bit ............................................................................5-12
5.4.2 RFO — Receive FIFO Overrun bit ..................................................5-12
5.4.3 TMS[5:4] — TransmITter Status FIEld ..............................................5-12
5.4.3.1 TransmITter Not Involved .........................................................5-12
5.4.3.2 TransmITter Underrun ..............................................................5-12
5.4.3.3 TransmITter Lost Arbitration .....................................................5-13
5.4.3.4 TransmITter Successful ............................................................5-13
5.4.4 IFR — In-Frame Response bit ........................................................5-13
5.4.5 IFRC — In-Frame Response CRC bit .............................................5-13
5.4.6 ERRC[1:0] — Error Code FIEld .......................................................5-13
5.4.6.1 CRC Error ...............................................................................5-13
5.4.6.2 Incomplete Byte Error .............................................................5-13
5.4.6.3 bit Timing Error .......................................................................5-14
5.4.6.4 BREAK Error ...........................................................................5-14
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
B.1 Pin Assignments ....................................................................................... B-1
5.5 Package Dimensions ................................................................................ B-3
B.2 Obtaining Updated MC68HC58 Mechanical Information ......................... B-4
B.3 Ordering Information ................................................................................ B-4
APPENDIX C DLC REGISTERS
C.1 Command Byte Register .......................................................................... C-1
C.2 Configuration Byte Register ..................................................................... C-2
C.3 Status Byte Register ................................................................................. C-3
C.4 Completion Code Byte Register ............................................................... C-4
1-1 MC68HC58 DLC Parallel Mode Block Diagram ............................................. 1-3
1-2 MC68HC58 DLC Serial Mode Block Diagram ................................................ 1-4
2-1 MC68HC58 DLC Pin Assignments ................................................................. 2-1
2-2 DLC Parallel Mode circuIT .............................................................................. 2-5
2-3 DLC Serial Mode circuIT ............................................................................... 2-10
2-4 Method 1 — Standby Mode Supplies ApplIEd .............................................. 2-14
2-5 Method 2 — Switching VDD wITh PSEN ....................................................... 2-15
2-6 Method 3 — SwITching VDD and VCC in Standby Mode ............................. 2-16
3-1 J1850 Bus Message Components ................................................................. 3-1
3-2 J1850 Bus Frame Format (VPW) ................................................................... 3-1
3-3 J1850 VPW Symbols ...................................................................................... 3-5
3-4 J1850 VPW Passive Symbols ........................................................................ 3-6
3-5 J1850 VPW Active Symbols ........................................................................... 3-8
3-6 J1850 VPW BITwise Arbitration ....................................................................... 3-9
4-1 DLC Operating Modes .................................................................................... 4-1
4-2 DLC Usage ..................................................................................................... 4-3
4-3 DLC Operation ............................................................................................... 4-5
4-4 Parallel Mode Byte Format ............................................................................. 4-6
4-5 DLC Serial Mode Byte Format ....................................................................... 4-8
4-6 SPI Transfer — Clock PolarITy Low .............................................................. 4-10
4-7 SPI Transfer — Clock PolarITy High ............................................................. 4-10
4-8 Host/DLC Serial Mode InITialization Routine ................................................ 4-11
4-9 Host/DLC Serial Mode TransmIT Routine (Part 1 of 2) ................................. 4-14
4-10 Host/DLC Serial Mode TransmIT Routine (Part 2 of 2) ................................. 4-15
4-11 Host/DLC Serial Mode Receive Routine (Part 1 of 2) .................................. 4-18
4-12 Host/DLC Serial Mode Receive Routine (Part 2 of 2) .................................. 4-19
A-1 Parallel Interface Timing .................................................................................A-3
A-2 SPI Timing — Active High SCLK ....................................................................A-5
A-3 SPI Timing — Active Low SCLK ....................................................................A-5
A-4 DLC Interrupt Timing ......................................................................................A-7
A-5 Reset Timing ..................................................................................................A-8
A-6 Variable Pulse-Width Modulation (VPW) Symbol Timings .............................A-9
B-1 MC68HC58 28-Pin PLCC ...............................................................................B-1
B-2 MC68HC58 28-Pin SOIC ...............................................................................B-2
B-3 Case Outline #776-02 ....................................................................................B-3
B-4 Case Outline #751F-04 ..................................................................................B-4
2-1 MC68HC58 DLC Parallel Mode Pin Function........................................................ 2-2
2-2 MC68HC58 DLC Serial Mode Pin Functions......................................................... 2-7
4-1 Parallel Transfers................................................................................................... 4-6
4-2 Minimum Time Between Operations...................................................................... 4-7
4-3 Serial Transfers ..................................................................................................... 4-9
4-4 IFR Error CondITions ............................................................................................ 4-22
5-1 General Command Summary................................................................................ 5-2
5-2 Byte Type and Destination Summary .................................................................... 5-4
5-3 RFC FIEld Encoding............................................................................................... 5-6
5-4 Internal Clock FrEQuency Derivations................................................................... 5-8
5-5 RFS FIEld Encoding.............................................................................................. 5-9
5-6 TMFS FIEld Encoding .......................................................................................... 5-11
5-7 TMS FIEld Encoding ............................................................................................ 5-12
5-8 ERRC FIEld Encoding......................................................................................... 5-13
A-1 Operating CondITions.............................................................................................A-1
A-2 Electrical Characteristics .......................................................................................A-2
A-3 Absolute Maximum Ratings...................................................................................A-2
A-4 Parallel Interface Parameters................................................................................A-4
A-5 Serial Interface Parameters...................................................................................A-6
A-6 Standby and Interrupt Timing................................................................................A-8
A-7 Reset Timing .........................................................................................................A-9
A-8 Transceiver REQuirements (DC)..........................................................................A-10
A-9 TransmITter VPW Symbol Timings ......................................................................A-10
A-10 Receiver VPW Symbol Timings ........................................................................A-10
B-1 MC68HC58 Ordering Information..........................................................................B-4
C-1 General Command Summary (GCOM).................................................................C-1
C-2 Byte Type and Destination Summary (BTAD).......................................................C-1
C-3 RFC FIEld Encoding (RFC) ...................................................................................C-1
C-4 Test Mode Control bit (TM)...................................................................................C-2
C-5 Test Configuration FIEld (TC)................................................................................C-2
C-6 Interrupt Mask bit (IMSK)......................................................................................C-2
C-7 Interrupt Mode bit (IMOD).....................................................................................C-2
C-8 Internal Clock FrEQuency FIEld (OSCD)................................................................C-2
C-9 High-Speed Control bit (4X)..................................................................................C-2
C-10 Receive FIFO Status FIEld Encoding (RFS) .......................................................C-3
C-11 Data Link Idle bit (DLI) ........................................................................................C-3
C-12 Network Fault bit (NETF) ....................................................................................C-3
C-13 4X Mode bit (4XMD) ...........................................................................................C-3
C-14 TransmIT FIFO Status FIEld Encoding (TMFS)....................................................C-3
C-15 Error bit (ERRF)..................................................................................................C-4
C-16 Receive FIFO Overrun bit (RFO)........................................................................C-4
C-17 TransmITter Status FIEld Encoding (TMS) ...........................................................C-4
C-18 In-Frame Response bit (IFR)..............................................................................C-4
C-19 In-Frame Response CRC bit (IFRC)...................................................................C-4
C-20 Error Code FIEld Encoding..................................................................................C-4

SECTION 1INTRODUCTION
The MC68HC58 DLC (data link controller) handles microcontroller unIT (MCU) to
Society of Automotive Engineers (SAE) J1850 bus interface dutIEs. The MC68HC58
DLC is the successor to the MC68HC56 DLCP (data link controller parallel) and the
MC68HC57 DLCS (data link controller serial). The MC68HC58 is pin configurable to
communicate wITh a host MCU via an 8-bit non-multiplexed parallel data bus or a
Motorola serial peripheral interface.
The DLC consists of control logic and bus transceiver circuITs.
Figure 1-1
shows the
internal structure of a DLC configured for parallel mode.
Figure 1-2
shows the internal
structure of a DLC configured for serial mode. The built-in bus transceiver allows the
DLC to be directly connected to the J1850 bus, thus providing a complete link between
the central processing unIT (CPU) host application and the J1850 bus. The J1850 bus
proTOCol is a method of information transfer via messages (frames) between nodes. A
node is any location on the J1850 bus that sends and receives messages.